Audio Control FOUR.1i Specifikace

   1FEATURESAPPLICATIONSDESCRIPTIONTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007FOUR-CHANNEL, LO

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007ELECTRICAL CHARACTERISTICS (continued)At 25 ° C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, D

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007ELECTRICAL CHARACTERISTICS (continued)At 25 ° C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, D

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007ELECTRICAL CHARACTERISTICS (continued)At 25 ° C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, D

www.ti.comAUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS (FOR A AND B INTERFACES)T0145-04WCLK_xBCLK_xDOUT_xDIN_xt (DO-BCLK)dt (DO-WS)dt (WS)dt (DI)St (DI

www.ti.comT0146-03WCLK_xBCLK_xDOUT_xDIN_xt (DO-BCLK)dt (WS)dt (WS)dt (DI)St (DI)hTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007All specifi

www.ti.comT0145-05WCLK_xBCLK_xDOUT_xDIN_xt (WS)ht (BCLK)Ht (DO-BCLK)dt (DO-WS)dt (DI)St (BCLK)Lt (DI)ht (WS)STLV320AIC34SLAS538A – OCTOBER 2007 – REVI

www.ti.comT0146-04WCLK_xBCLK_xDOUT_xDIN_xt (WS)ht (WS)ht (BCLK)Lt (DO-BCLK)dt (DI)St (BCLK)Ht (DI)ht (WS)St (WS)STLV320AIC34SLAS538A – OCTOBER 2007 –

www.ti.comTYPICAL CHARACTERISTICS-90-80-70-60-50-40-30-20-1000 20 40 60 80 100HeadphoneOutPower-mWTHD-TotalHarmonicDistortion-dB3.6VDD_CM1

www.ti.com-160-140-120-100-80-60-40-2000 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20f-Frequency-kHzAmplitude-dBLoad=10k ,FS=48kHz,

www.ti.com-160-140-120-100-80-60-40-2000 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20f-Frequency-kHzAmplitude-dBLoad=10k ,FS=48kHz,

www.ti.comDESCRIPTION (CONTINUED)TLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007These devices have limited built-in ESD protection. The lea

www.ti.comMICBIAS_A2kW0.47 FmAVDD_DACAVSS_DACDRVDDDRVSSPVDDDRVDDDRVSSAVDD_ADCAVSS_DACAIOVDDAAVDD4700pF4700pF560 W560 W560 W560 WAAVBAT1 FmPVSSTPA2012

www.ti.comMICBIAS_B2kWDOUT_BADDR_BBCLK_BDIN_BMCLK_BWCLK_BMIC3L_BLEFT_LOP_BLEFT_LOP_BLEFT_LOM_BLEFT_LOM_BLINE2LP_BLINE2LM_BMONO_LOP_AMONO_LOM_AMicroph

www.ti.comOVERVIEWHARDWARE RESETDIGITAL CONTROL SERIAL INTERFACETLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007The TLV320AIC34 is a highly

www.ti.comI2C CONTROL MODESDASCLtHD-STA0.9 s³ mtSU-STO0.9 s³ mPStSU-STA0.9 s³ mSrtHD-STA0.9 s³ mST0114-02TLV320AIC34SLAS538A – OCTOBER 2007 – REVISED

www.ti.comDA(6) DA(0) RA(7) RA(0) D(7) D(0)T0147-01SDASCL(M) – SDA ControlledbyMaster(S) – SDA ControlledbySlaveStart(M)Write(M)SlaveAck(S)SlaveAc

www.ti.comI2C BUS DEBUG IN A GLITCHED SYSTEMDIGITAL AUDIO DATA SERIAL INTERFACEAudioSerialDataBusDOUT_xDIN_xBCLK_xWCLK_xGPIO2_xGPIO1_xB0233-01TLV32

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007The data busses of the TLV320AIC34 can be configured for left- or right-justified,

www.ti.comRIGHT-JUSTIFIED MODEBCLK_xWCLK_x10010T0149-031/fsLSBMSBLeftChannelRightChannel2 2DIN_x/DOUT_xn nn–1 n–1n–2n–2LEFT-JUSTIFIED MODEBCLK_xWCLK

www.ti.comI2S MODEBCLK_xWCLK_x1 10 0T0151-031/fsLSBMSBLeftChannelRightChannel2 2DIN_x/DOUT_xn n n1ClockBeforeMSBn–1 n–1n–2 n–2DSP MODEBCLK_xWCLK_

www.ti.comTDM DATA TRANSFERN–1N–1N–11111N–1N–2N–2N–20000N–2Right-ChannelDataRight-ChannelDataLeft-ChannelDataLeft-ChannelData••••••••••••

www.ti.comSIMPLIFIED BLOCK DIAGRAMI CSerial2ControlBusVoltageSuppliesRIGHT_LOP_ARIGHT_LOM_ALEFT_LOP_ALEFT_LOM_AMONO_LOP_AMONO_LOM_AHPROUT_AHPRCOM_A

www.ti.comAUDIO DATA CONVERTERSAUDIO CLOCK GENERATIONTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007The TLV320AIC34 supports the following

www.ti.com(K R) / P´PLL_CLKINCODECCODEC_CLKINPLL_OUTMCLK_x BCLK_xPLL_INB0153-02DAC fSADC fSCODEC_CLK=256 f´S(ref)CLKDIV_OUT1/8PLLDIV_OUTCLKDIV_CLKIN

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007NOTE – when NDAC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007The following table lists several example cases of typical MCLK rates and how to p

www.ti.comSTEREO AUDIO ADCSTEREO AUDIO ADC HIGH-PASS FILTERH(z) +N0 ) N1 z*132768 * D1 z*1(1)DIGITAL AUDIO PROCESSING FOR RECORD PATHTLV320AIC34SL

www.ti.comDigital AudioDataSerialInterfaceADC++DIN_xDOUT_xBCLK_xWCLK_xDINLDINRDOUTLDOUTRADCAGCAGCRecordPathRecordPathEffectsEffectsSW-D1SW-D2SW-D

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Attack time determines how quickly the AGC circuitry reduces the PGA gain when the

www.ti.comDecay TimeTargetLevelInputSignalOutputSignalAGCGainAttackTimeSTEREO AUDIO DACTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Figur

www.ti.comDIGITAL AUDIO PROCESSING FOR PLAYBACKH(z) +N0 ) N1 z*132768 * D1 z*1(2)ǒN0 ) 2 N1 z*1) N2 z*232768 * 2 D1 z*1* D2 z*2ǓǒN3 )

www.ti.comB0155-01LB1RB2AttenLB2L+++++––++RToLeftChannelToRightChannelDIGITAL INTERPOLATION FILTERTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOV

www.ti.comTERMINAL ASSIGNMENTSLKJHGFEDCBA1 23456 7 8 9 1011ZASPackage(TopView)P0061-01TLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Tabl

www.ti.comDELTA-SIGMA AUDIO DACAUDIO DAC DIGITAL VOLUME CONTROLINCREASING DAC DYNAMIC RANGEANALOG OUTPUT COMMON-MODE ADJUSTMENTTLV320AIC34SLAS538A – O

www.ti.comAUDIO DAC POWER CONTROLAUDIO ANALOG INPUTSGain=0, –1.5, –3,..., –12dB,MuteToLeft ADCPGAB0156-03LINE1LP_xLINE1RM_xGain=0, –1.5, –3

www.ti.comGain=0, –1.5, –3,..., –12dB,MuteGain=0, –1.5, –3,..., –12dB,MuteToLeft ADCPGAB0156-04LINE2LP_xMIC3L_xGain=0, –1.5, –3,..

www.ti.comADC PGA SIGNAL BYPASS PATH FUNCTIONALITYINPUT IMPEDANCE AND VCM CONTROLPASSIVE ANALOG BYPASS DURING POWER DOWNTLV320AIC34SLAS538A – OCTOBER

www.ti.comLEFT_LOP_xRIGHT_LOP_xLEFT_LOM_xRIGHT_LOM_xSW-L0SW-R0SW-L3SW-R3SW-L1SW-R1SW-L4SW-R4SW-L2SW-R2LINE1LP_xLINE2RP_xLINE1LM_xLINE2RM_xLINE1LP_xLIN

www.ti.comDIGITAL MICROPHONE CONNECTIVITYANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERSTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007The TL

www.ti.comB0157-03DAC_LDAC_L1DAC_L2DAC_L3DAC_RDAC_R1DAC_R2DAC_R3LEFT_LOP_xLEFT_LOM_xStereoAudioDACVolumeControls,MixingGain=0dBto9dB,MuteLINE2LP

www.ti.com0dBto –78dB0dBto –78dB+DAC_L1DAC_R1B0158-030dBto –78dBLINE2LP_xLINE2LM_x0dBto –78dBPGA_RP_xPGA_RM_x0dBto –78dBPGA_LP_xPGA_LM_

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007• Combinations of the foregoingThe output-stage architecture of each partition lea

www.ti.comVCMVCMHPLOUT_xHPLCOM_xHPRCOM_xHPROUT_xDAC_L2DAC_R2B0159-03VolumeLevel0dBto9dB,MuteVolumeLevel0dBto9dB,MuteVolumeLevel0dBto9

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Table 1. TERMINAL FUNCTIONS, ALPHABETIC (continued)TERMINALI/O DESCRIPTIONNAME BGA

www.ti.comSHORT-CIRCUIT OUTPUT PROTECTIONJACK/HEADSET DETECTIONTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007The high-power output drivers

www.ti.comMICBIAS_xMIC3L_xorMIC3R_xHPLOUT_xHPROUT_xToDetectionBlockHPRCOM_xHPLCOM_xVCMMICDET_xToDetectionBlockssg msg mssgStereoCellularStereo+Cel

www.ti.comToDetectionblockHPLOUT_xHPLCOM_xHPROUT_xHPRCOM_xMICDET_xThisswitchcloseswhenjackisremovedB0245-01CONTROL REGISTERSTLV320AIC34SLAS538A

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 1: Software Reset RegisterREAD/ RESETBIT DESCRIPTIONWRITE VALUED

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 4: PLL Programming Register BREAD/ RESETBIT DESCRIPTIONWRITE VAL

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 8: Audio Serial Data Interface Control Register AREAD/ RESETBIT

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 10: Audio Serial Data Interface Control Register CREAD/ RESETBIT

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 12: Audio Codec Digital Filter Control RegisterREAD/ RESETBIT DE

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 14: Headset / Button Press Detection Register BREAD/ RESETBIT DE

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 17: MIC3L_x and MIC3R_x to Left-ADC Control RegisterREAD/ RESETB

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Table 1. TERMINAL FUNCTIONS, ALPHABETIC (continued)TERMINALI/O DESCRIPTIONNAME BGA

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 19: LINE1LP_x and LINE1LP_x and LINE1LM_xM_x to Left-ADC Control

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 21: LINE1RP_x and LINE1RM_x to Left-ADC Control RegisterREAD/ RE

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 23: LINE2RP_x and LINE2RM_x to Right-ADC Control RegisterREAD/ R

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 25: MICBIAS_x Control RegisterREAD/ RESETBIT DESCRIPTIONWRITE VA

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 28: Left-AGC Control Register CREAD/ RESETBIT DESCRIPTIONWRITE V

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 31: Right-AGC Control Register CREAD/ RESETBIT DESCRIPTIONWRITE

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 34: Left-AGC Noise Gate Debounce RegisterREAD/ RESETBIT DESCRIPT

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 36: ADC Flag RegisterREAD/ RESETBIT DESCRIPTIONWRITE VALUED7 R 0

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 38: High-Power Output Driver Control RegisterREAD/ RESETBIT DESC

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 41: DAC Output Switching Control RegisterREAD/ RESETBIT DESCRIPT

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Table 2. TERMINAL FUNCTIONS, NUMERIC (continued)TERMINALI/O DESCRIPTIONBGA BALL NA

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 44: Right-DAC Digital Volume Control RegisterREAD/ RESETBIT DESC

www.ti.comOutput Stage Volume ControlsTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007A basic analog volume control with range from 0 dB to

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 46: PGA_LP_x and PGA_LM_x to HPLOUT_x Volume Control RegisterREA

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 51: HPLOUT_x Output Level Control RegisterREAD/ RESETBIT DESCRIP

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 55: LINE2RP_x and LINE2RM_x to HPLCOM_x Volume Control RegisterR

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 59: LINE2LP_x and LINE2LM_x to HPROUT_x Volume Control RegisterR

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 65: HPROUT_x Output Level Control RegisterREAD/ RESETBIT DESCRIP

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 69: LINE2RP_x and LINE2RM_x to HPRCOM_x Volume Control RegisterR

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 73: LINE2LP_x and LINE2LM_x to MONO_LOP_x and MONO_LOM_x Volume

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 78: DAC_R1 to MONO_LOP_x and MONO_LOM_x Volume Control RegisterR

www.ti.comABSOLUTE MAXIMUM RATINGSDISSIPATION RATINGS(1)RECOMMENDED OPERATING CONDITIONSTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007over

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 82: DAC_L1 to LEFT_LOP_x and LEFT_LOM_x Volume Control RegisterR

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 86: LEFT_LOP_x and LEFT_LOM_x Output Level Control RegisterREAD/

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 90: LINE2RP_x and LINE2RM_x to RIGHT_LOP_x and RIGHT_LOM_x Volum

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 94: Module Power-Status RegisterREAD/ RESETBIT DESCRIPTIONWRITE

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 96: Sticky Interrupt Flags RegisterREAD/ RESETBIT DESCRIPTIONWRI

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 98: GPIO1_x Control RegisterREAD/ RESETBIT DESCRIPTIONWRITE VALU

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 99: GPIO2_x Control RegisterREAD/ RESETBIT DESCRIPTIONWRITE VALU

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 101: Codec A, I2C Address SelectREAD/ RESETBIT DESCRIPTIONWRITE

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 104: Left-AGC New Programmable Decay Time Register(1)READ/ RESET

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 106: Right-AGC New Programmable Decay Time Register(1)READ/ RESE

www.ti.comELECTRICAL CHARACTERISTICSTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007At 25 ° C, AVDD_DAC, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V,

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Page 0 / Register 108: Passive Analog Signal Bypass Selection During Power Down Re

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007The remaining page-1 registers are either reserved registers or are used for setti

www.ti.comTLV320AIC34SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007Table 8. Page-1 Registers (continued)REGISTERRESET VALUE REGISTER NAMENUMBER38 010

PACKAGE OPTION ADDENDUMwww.ti.com21-Jan-2014Addendum-Page 1PACKAGING INFORMATIONOrderable Device Status(1)Package Type PackageDrawingPins PackageQtyEc

PACKAGE OPTION ADDENDUMwww.ti.com21-Jan-2014Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total pur

TAPE AND REEL INFORMATION*All dimensions are nominalDevice PackageTypePackageDrawingPins SPQ ReelDiameter(mm)ReelWidthW1 (mm)A0(mm)B0(mm)K0(mm)P1(mm)W

*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)TLV320AIC34IZASR NFBGA ZAS 87 2500 336.6 336

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherch